Quartus Project setup
Last Update: 2023-10-28
The starter code for the quartus project is available below. This already does the device selection and pin assignment but is otherwise empty. Feel free to do this yourself if you want the experience or are using a different device from the MAX 10 DE10-lite boards.
de10_lite.zip starter files
> Getting Started
In the starter code directory, locate the .qpf file. This is a Quartus Project File which is used for configuring the project, the asspicated pins, soure files, etc. We will open this with Quartus.
The first time that you launch Quartus, you’ll have to tell if you have a license—you don’t (if you're on your own machine).

Press “OK” then once the full window opens, select “Open Project”

Navigate to the location that you generated the project from the System Builder and select the “.qpf” file.

On the left-hand pane, the image shows a de10_lite file. Double click on it and the text editor should open it. This is your project’s top-level module file. You can use this for connecting each of your modules to the IO pins.
To add more modules, create a separate Verilog for for each then add them to the project.
> Adding Your Code
To add your modules (in files) to the project, go to Project > Add/Remove Files in Project…

The next window that open should have a “File Name” field. Press the “…” button and browse to where your Verilog source files are located.

Once added, the files should appear in the file list:

Press “OK” to close the file window.
> Instantiating Your Modules
With your top level module opened (double click it in the left-hand pane), add an instantiation of your module under the “Structural Coding” section. (This looks like an ordinary Verilog instantiation of any other module.)

Note how the IO ports of the top-level module are connected the instantiated module through the array indexing of each of the vectors.
> Synthesizing Your Design
Once you believe that your design is functional (you should test it with a sim – it will save you a lot of time), press the Start Compilation (Ctrl+L) button.

Compilation messages will be listed in the bottom message pane. If there are any errors during the process, they will show up here.

You can tell that compilation is complete when the left-hand tasks pane has all green checkmarks.
> Programming (Uploading) the Bitstream Configuration
First, make sure the board is plugged into your computer and is detected. To upload the synthesized bit stream, you should click on the Programmer button in the top toolbar.

Then the programmer window should pop up.

Click on the “Hardware Setup” button and in the new window, select the USB-Blaster from the drop-down menu.
Click “Close” when done.

Next, press “Auto Detect” on the programmer window.
Right click the 10M50DAF484 and select “Change File…”. Browse to the project folder and locate the .sof file.

Your programmer window should now look like this:

Make sure that the 10M50DAF484 has a checkmark in the Program/Configure column but none of the other boxes are checked. At this point, you should be able to press “Start” and your code will upload. (If Quartus crashes—and it often does at this step—just reopen and try again.)